1. Field of the Invention
This invention relates generally to static memory devices and, more particularly, to a four device static random access memory device having a single bitline.
2. Discussion of the Related Art
Various configurations of static random access memory (SRAM) memory cells have been designed/developed to reduce silicon area by eliminating devices where smaller array size is needed. FIG. 1 illustrates a basic six transistor full CMOS SRAM cell 10, as is known in the art. Data is stored in the cell 10 as voltage levels with the two sides of a bistable transistor flip-flop (i.e., latch) in opposite voltage configurations. For example, node A is high and node B is low in one state; whereas, node A is low and node B is high in the opposite state resulting in two stable states (i.e., bistable).
One approach taken to reduce the basic six transistor full CMOS cell is shown in FIG. 2. FIG. 2 shows a single-ended five transistor static CMOS cell 20. The five transistor CMOS cell 20 contains one less transistor and one less bitline per cell than the more common six transistor cell. In the five transistor configuration, writing a `1` into the cell 20 is difficult because the transistor T5 separating the cell from the bitline (i.e., the transfer transistor) operates in a source follower mode, thereby limiting the voltage transferred from the bitline to the cell's internal node B. With the charge transfer from the bitline alone, it is difficult to overwrite a previously written `0` in the cell to a `1`.
Another approach taken to reduce the basic six transistor CMOS cell is shown in FIG. 3. FIG. 3 illustrates a four transistor static cell 30 with resistor load pull-up devices R0,R1, further referred to as an R-load SRAM cell. This cell configuration reduces the cell size of the more common six device SRAM by two transistors. However, the resulting cell 30 has higher current leakage when not being accessed (i.e., in a standby mode) than the six transistor full CMOS SRAM cell, since a small amount of current always flows through the resistors R0,R1. For any of the two given stable states within the cell 30, one resistor functions to pull-up and offset the charge leakage of the drains of the storage and transfer transistors while the other resistor functions as a load to limit the current to the low (`0`) node.
Continuing with the above evolution in cell device reduction, the next logical reduction would be to reduce the number of transistors to three, one less than the R-load SRAM cell 30 previously discussed. FIG. 4 shows one such cell configuration in which three transistors Q4,Q5,Q6 are used to create a single ended three device R-load cell 40. The single ended three device R-load cell 40 configuration shares the same concerns common to the five device CMOS SRAM cell 20 discussed earlier. In addition to writing a `1`, the cell configuration 40 of FIG. 4 also has difficulty in writing a `0` reliably, if at all. The passive resistors R0,R1 of the three device R-load cell 40 must be very high, in the range of 10 to 100 G ohms, to keep a standby power dissipation as low as possible. Therefore, the recovery time of these resistors is far too slow to adequately pull-up and/or maintain stable high levels within the cell 40.
It is thus desirable to provide a smaller SRAM cell with a minimum impact on performance.